Fast LDPC GPU Decoder for Cloud RAN

被引：9

作者：

Ling, Jonathan ^{[1
]}

Cautereels, Paul ^{[2
]}

机构：

[1] Nokia Bell Labs, Wireless Access Lab, Murray Hill, NJ 07974 USA

[2] Nokia Bell Labs, Wireless Access Lab, B-2018 Antwerp, Belgium

来源：

IEEE EMBEDDED SYSTEMS LETTERS | 2021年 / 13卷 / 04期

关键词：

5G wireless; forward error correction; graphics processors; low-density parity check (LDPC); CODES;

D O I：

10.1109/LES.2021.3052714

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The graphical processing unit (GPU), as a digital signal processing accelerator for cloud RAN, is investigated. This letter presents a new design for a 5G NR low-density parity check code decoder running on a GPU. The algorithm is flexibly adaptable to GPU architecture to achieve high resource utilization as well as low latency. It improves on the layered algorithm by increasing parallelism on a single code word. The flexible GPU decoder (on a 24 core GPU) was found to have 5x higher throughput compared to a recent GPU flooding decoder and 3x higher throughput compared to a field programmable gate array (FPGA) decoder (757K gate). The flexible GPU decoder exhibits 1/3 decoding power efficiency of the FPGA typical of general-purpose processors. For rapid deployment and flexibility, GPUs may be suitable as cloud RAN accelerators.

引用

页码：170 / 173

页数：4