Congestion aware low power on chip protocols with network on chip with cloud security

被引:1
|
作者
Ponnan, Suresh [1 ]
Kumar, Tikkireddi Aditya [1 ]
Vs, Hemakumar [1 ]
Natarajan, Sakthieswaran [2 ]
Shah, Mohd Asif [3 ]
机构
[1] Vel Tech Rangarajan Dr Sagunthala R&D Inst Sci &, Dept ECE, Chennai, Tamil Nadu, India
[2] EGS Pillai Engn Coll, Dept Civil Engn, Nagapattinam, Tamil Nadu, India
[3] Kebri Dehar Univ, Kebri Dehar, Ethiopia
关键词
Network-on-Chip; System on Chip; Chip multiprocessor; Congestion; Long term evolution; Embedded transition inversion; Very Large Scale Integration; ROUTING METHOD; PERFORMANCE; MODEL;
D O I
10.1186/s13677-022-00307-4
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This article is to analyze the bottleneck problems of NoC in many more applications like multi-processor communication, computer architectures, and network interface processors. This paper aims to research the advantages and disadvantages of low congestion protocols on highway environments like multiple master multiple slave interconnections. A long-term evolution and effective on-chip connectivity solution for secured, congestion aware and low power architecture is emerged for Network-on-Chip (NoC) for MCSoC. Applications running simultaneously on a different chip are often exchanged dynamically on the chip network. Of-course, in general on chip communication, resources mean that applications may interact with shared resources to influence each other's time characteristics.
引用
收藏
页数:10
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