Testing approach within FPGA-based fault tolerant systems

In this paper, we propose a test strategy for FPGA to be applied within FPGA based fault tolerant systems. We propose to mate some CLBs under test and to implement the rest of CLBs with the normal user data. In the target fault tolerant systems, there is two phases (functional phase and the test phase). In the functional phase the system achieves its normal functionality. While in the test phase the FPGA is tested. In this phase, the configuration data of CLBs under test are shifted on chip in parallel to other CLBs for achieving the best in these CLBs. In one test phase the whole CLBs are tested. The shifting process control, test application, and best observation are achieved by the logic managing the fault tolerance (from outside the chip). The system returns to its normal phase after all CLBs are scanned by the test. The application of this approach reduces the fault tolerance cost (hardware, software, time,..etc). The user will be able to test periodically the chip using only the data inside the chip and without destroying the original configuration data. No particular hardware is required for saving onboard the test data. Additionally no particular software treatment is required for the test. The test dime is decreased enormously. Unfortunately as a consequence of implementing two types of data on-chip, 15% decrease of the chip functionality and 2.5% delay overhead are noticed in the case of structures similar to 20 x 20 Xilinx FPGA.