Manufacturing a CSP at wafer level

The CSP (Chip Size or Chip Scale Package) is miniaturised package which is an alternative to COB (Chip on Board) and DCA (Direct Chip Attach/Flip Chip). Manufacturing CSP's at waferlevel becomes a challenging task to reduce package cost. A major issue in chip size packaging is the board level reliability, because the package has to match the different CTE's of silicon and PCB (3 ppm/K versus 16-18 ppm/K), In contrast to flip chip technology no underfilling should be required. Therefore a wafer level package (WLP) needs a stress absorbing construction to avoid underfilling. A wafer level CSP called S-3-Diepack was developed at Technical University of Berlin within the European ESPRIT project ESCHETA. The S-3-Diepack uses a solder support structure (S-3) to avoid underfilling. The S-3-Diepack achieves a board level reliability which may be sufficient for consumer products.