A 60 GHz-Standard Compatible Programmable 50 GHz Phase-Locked Loop in 90 nm CMOS

被引：12

作者：

Barale, F. ^{[1
]}

Sen, P. ^{[1
]}

Sarkar, S. ^{[1
]}

Pinel, S. ^{[1
]}

Laskar, J. ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30308 USA

来源：

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2010年 / 20卷 / 07期

关键词：

CMOS integrated circuits; frequency divider; millimeter-wave circuits; phase-locked loop (PLL);

D O I：

10.1109/LMWC.2010.2049444

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter presents, for the first time, a 60 GHz four-channel standard compatible heterodyne frequency synthesizer solution with low-cost reference signal. The presented PLL features a dual-core varactor-based LC cross-coupled voltage-controlled oscillator (VCO). The measured phase noise is -80.1 dBc/Hz at 1 MHz offset, and it is limited by the phase noise of the reference signal. The measured output spectrum shows spur suppression higher than 32 dBc. Using the lowest reference frequency to date (27 MHz), the presented PLL is suitable for applications in low cost fully integrated multi-gigabit 60 GHz CMOS radio transceivers.

引用

页码：411 / 413

页数：3

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