Single edge clock (SEC) distribution for improved latency, skew, and jitter performance

Synchronous clock distribution continues to be the dominant timing methodology for VLSI designs. As processes shrink, clock speeds increase, and die sizes grow, more-and-more of the clock period is lost to skew and jitter budgets. We propose to improve clock performance by focusing on the single, critical clock edge while relaxing requirements of the non-critical edge. A novel re-design of the traditional clock buffer is proposed as a drop-in replacement for existing clock distribution networks, yielding timing performance improvements of over 20% in latency and skew and up to 30% in jitter; alternatively, these timing advantages could be traded off to reduce clock buffer area and power by 33% and 12%, respectively.