Advances, Challenges and Opportunities in 3D CMOS Sequential Integration

被引：0

作者：

Batude, P. ^{[1
]}

Vinet, M. ^{[1
]}

Previtali, B. ^{[1
]}

Tabone, C. ^{[1
]}

Xu, C. ^{[1
]}

Mazurier, J. ^{[1
]}

Weber, O. ^{[1
]}

Andrieu, F. ^{[1
]}

Tosti, L. ^{[1
]}

Brevard, L. ^{[1
]}

Sklenard, B. ^{[1
,2
]}

Coudrain, P. ^{[2
]}

Bobba, S. ^{[3
]}

Ben Jamaa, H. ^{[1
]}

Gaillardon, P-E. ^{[1
]}

Pouydebasque, A. ^{[1
]}

Thomas, O. ^{[1
]}

Le Royer, C. ^{[1
]}

Hartmann, J. -M. ^{[1
]}

Sanchez, L. ^{[1
]}

Baud, L. ^{[1
]}

Carron, V. ^{[1
]}

Clavelier, L. ^{[1
]}

De Micheli, G. ^{[3
]}

Deleonibus, S. ^{[1
]}

Faynot, O. ^{[1
]}

Poiroux, T. ^{[1
]}

机构：

[1] CEA Leti, Minatec Campus, F-38054 Grenoble, France

[2] ST Microelect, F-38926 Crolles, France

[3] Ecole Polytech Fed Lausanne, Lausanne, Switzerland

来源：

2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2011年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600 degrees C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications.

引用

页数：4

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