Energy-efficient capacitor-splitting DAC scheme with high accuracy for SAR ADCs

被引：28

作者：

Xie, Liangbo ^{[1
]}

Su, Jian ^{[1
]}

Liu, Jiaxin ^{[1
]}

Wen, Guangjun ^{[1
]}

机构：

[1] Univ Elect Sci & Technol China, Ctr RFIC & Syst Technol, Sch Commun & Informat Technol, Chengdu 611731, Peoples R China

来源：

ELECTRONICS LETTERS | 2015年 / 51卷 / 06期

关键词：

frequency dividers; CMOS integrated circuits; circuit feedback; field effect transistors; mixers (circuits); field effect MMIC; enhanced locking range technique; divide-by-3 differential injection-locked frequency divider; CMOS; transformer feedback; conversion efficiency; injection metal-oxide semiconductor field-effect transistor mixers; ILFD core; size; 0; 18; mum; power; 10; 8; mW; voltage; 9; V; current; 12; mA; frequency; 4; 2 GHz to 13; GHz; SWITCHING SCHEME;

D O I：

10.1049/el.2015.0008

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An energy-efficient capacitor-splitting digital-to-analogue converter (DAC) scheme with high-accuracy for successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. The proposed method uses a split-capacitive-array DAC structure and optimises the switching energy during conversion using energy-efficient 'up' transition. The proposed switching scheme achieves a 96.91% switching energy reduction and a 75% area reduction compared with the conventional method. In addition, the third reference voltage (V-cm) has no effect on the accuracy of the SAR ADC except the least significant bit, resulting in a good trade-off between the energy-efficiency and accuracy of the ADC.

引用

页码：460 / 461

页数：2

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