Electrical instability of hydrogenated amorphous silicon thin-film transistors for active-matrix liquid-crystal displays

We investigated the threshold voltage shifts (Delta V-T) of inverted-staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) induced by steady-state (dc) and pulsed (ac) gate bias-temperature-stress (BTS) conditions. Our study showed that, for an equivalent effective-stress-time, Delta V-T has an apparent pulse-width dependence under negative ETS conditions-the narrower the pulse width, the smaller the Delta V-T. This gate-bias pulse-width dependence is explained by an effective-carrier-concentration model, which relates Delta V-T for negative pulsed gate-bias stress to the concentration of mobile carriers accumulated in the conduction channel along the a-Si:H/gate insulator interface. in addition, our investigation of the methodology of a-Si:H TFT electrical reliability evaluation indicates that, instead of steady-state BTS, pulsed BTS should be used to build the database needed to extrapolate Delta V-T induced by a long-term display operation. Using these experimental results. we have shown that a-Si:H TFTs have a satisfactory electrical reliability for a Icing-term active-matrix liquid-crystal display (AMLCD) operation.