GRAM: Graph Processing in a ReRAM-based Computational Memory

被引:33
|
作者
Zhou, Minxuan [1 ]
Imani, Mohsen [1 ]
Gupta, Saransh [1 ]
Kim, Yeseong [1 ]
Rosing, Tajana [1 ]
机构
[1] Univ Calif San Diego, Comp Sci & Engn, La Jolla, CA 92093 USA
关键词
D O I
10.1145/3287624.3287711
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The performance of graph processing for real-world graphs is limited by inefficient memory behaviours in traditional systems because of random memory access patterns. Offloading computations to the memory is a promising strategy to overcome such challenges. In this paper, we exploit the resistive memory (ReRAM) based processing-in-memory (PIM) technology to accelerate graph applications. The proposed solution, GRAM, can efficiently executes vertex-centric model, which is widely used in large-scale parallel graph processing programs, in the computational memory. The hardware-software co-design used in GRAM maximizes the computation parallelism while minimizing the number of data movements. Based on our experiments with three important graph kernels on seven real-world graphs, GRAM provides 122.5x and 11.1x speedup compared with an in-memory graph system and optimized multi-threading algorithms running on a multi-core CPU. Compared to a GPU-based graph acceleration library and a recently proposed PIM accelerator, GRAM improves the performance by 7.1x and 3.8x respectively.
引用
收藏
页码:591 / 596
页数:6
相关论文
共 50 条
  • [21] Data Pruning-enabled High Performance and Reliable Graph Neural Network Training on ReRAM-based Processing-in-Memory Accelerators
    Ogbogu, Chukwufumnanya
    Joardar, Biresh
    Chakrabarty, Krishnendu
    Doppa, Jana
    Pande, Partha Pratim
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2024, 29 (05)
  • [22] ReRAM-based In-Memory Computation of Galois Field arithmetic
    Mandal, Swagata
    Bhattacharjee, Debjyoti
    Tavva, Yaswanth
    Chattopadhyay, Anupam
    PROCEEDINGS OF THE 2018 26TH IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2018, : 1 - 6
  • [23] PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration
    Yang, Tao
    Li, Dongyue
    Han, Yibo
    Zhao, Yilong
    Liu, Fangxin
    Liang, Xiaoyao
    He, Zhezhi
    Jiang, Li
    2021 58TH ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2021, : 583 - 588
  • [24] ReGNN: A ReRAM-based Heterogeneous Architecture for General Graph Neural Networks
    Liu, Cong
    Liu, Haikun
    Jin, Hai
    Liao, Xiaofei
    Zhang, Yu
    Duan, Zhuohui
    Xu, Jiahong
    Li, Huize
    PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC 2022, 2022, : 469 - 474
  • [25] CRPIM: An efficient compute-reuse scheme for ReRAM-based Processing-in-Memory DNN accelerators
    Hong, Shihao
    Chung, Yeh-Ching
    JOURNAL OF SYSTEMS ARCHITECTURE, 2024, 153
  • [26] Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures
    Arka, Aqeeb Iqbal
    Joardar, Biresh Kumar
    Doppa, Janardhan Rao
    Pande, Partha Pratim
    Chakrabarty, Krishnendu
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 29 (10) : 1743 - 1756
  • [27] LSTMs for Keyword Spotting with ReRAM-based Compute-In-Memory Architectures
    Schaefer, Clemens J. S.
    Horeni, Mark
    Taheri, Pooria
    Joshi, Siddharth
    2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2021,
  • [28] RED: A ReRAM-based Deconvolution Accelerator
    Fan, Zichen
    Li, Ziru
    Li, Bing
    Chen, Yiran
    Li, Hai
    2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2019, : 1763 - 1768
  • [29] ReCSA: a dedicated sort accelerator using ReRAM-based content addressable memory
    Li, Huize
    Jin, Hai
    Zheng, Long
    Huang, Yu
    Liao, Xiaofei
    FRONTIERS OF COMPUTER SCIENCE, 2023, 17 (02)
  • [30] A Weighted Sensing Scheme for ReRAM-based Cross-point Memory Array
    Liu, Chenchen
    Li, Hai
    2014 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2014, : 65 - 70