Leveraging new SEMI standard to reduce waste and improve flow for semicoductor manufacturing

A successful cutting-edge semiconductor manufacturer applies Lean principles with the goal set on perfecting its operation flow. In 2007 SEMI adopted a new standard E94-1107 that breaks the dependency between carrier and lot for processing wafers and formally introduces material redirection, which creates several opportunities for waste reductions and improved WIP handling. As depicted from simulations, the new standard is impacting several KPIs including throughput, cycle time, yield, and Just-In-Time customer response. This paper discusses different lean optimizations leveraging the new standard. Some tools require loading of many wafers simultaneously to achieve a high throughput. Although with reducing lot sizes, takt time can be improved, the sequential nature of these tools become limited by the number of load ports and thus have a negative impact on the equipment effectiveness. Before the new standard implementation, no carrier could be removed from load ports during processing to allow other carriers to load or unload wafers leaving the ports blocked. With this change, we can now remove the carrier from the Load Port after unloading wafers into the tool to allow filling the tool with the optimum number of wafers. Over the years, numerous lean manufacturing studies have been performed in terms of determining the correct lot size (number of wafers in a lot) to meet the Just-In-Time targets. Simulation runs demonstrate that smaller lots have up to 33% and 50% improved cycle time for batch tools and single wafer tools, respectively. Based on fluctuations in demand, there may not only be a need to speed up, but also to slow down production quickly. All these have direct correlation with scheduling of right sized lots (dynamic lot sizing), carefully planned delivery of carriers for processing and improved pull production techniques. (C) 2010 Elsevier Ltd. All rights reserved.