Impedance Calculation Methodology for Fault Simulation of Analog and Mixed-signal Circuits

被引：0

作者：

Brenkus, Juraj ^{[1
]}

Stopjakova, Viera ^{[1
]}

Arbet, Daniel ^{[1
]}

Gyepes, Gabor ^{[1
]}

Majer, Libor ^{[1
]}

机构：

[1] Slovak Univ Technol Bratislava, Inst Elect & Photon, Dept IC Design & Test, Bratislava, Slovakia

来源：

2014 24TH INTERNATIONAL CONFERENCE RADIOELEKTRONIKA (RADIOELEKTRONIKA 2014) | 2014年

关键词：

impedance calculation; analog circuit; fault analysis; NETWORKS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel impedance fault simulations methodology is presented in this paper. This methodology is based on an equation that calculates two-point impedance using the eigenvalues and eigenvectors of the circuit's nodal admittance matrix. This approach is applicable to active and passive circuits in both DC and AC domains. Possible applications of the proposed methods in the design of integrated circuits are presented as well.

引用

页数：4

共 14 条

[1]

Arabi K., 1996, VLSI TEST S, P476

[2]

Arbet D., 2013, NANOTECHNOLOGY IEEE, P1

[3]

Brenkus J, 2013, IEEE INT SYMP DESIGN, P170, DOI 10.1109/DDECS.2013.6549811

[4]

Cernanova V., 2013, NONSYMMETRIC FINITE

[5]

Chang CL, 2012, ASIA S PACIF DES AUT, P163, DOI 10.1109/ASPDAC.2012.6164938

[6] Coefficient-based test of parametric faults in analog circuits [J].

Guo, Z ;

Savir, J .

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2006, 55 (01) :150-157

[7]

Hu G., 2007, TSINGHUA SCI TECHNOL, V12, P78, DOI DOI 10.1016/S1007-0214(07)70088-3

[8] Practical oscillation-based test of integrated filters [J].

Huertas, G ;

Vázquez, D ;

Peralías, EJ ;

Rueda, A ;

Huertas, JL .

IEEE DESIGN & TEST OF COMPUTERS, 2002, 19 (06) :64-72

[9] Analog Circuit Fault Detection Using Location of Poles [J].

Kavithamani, Ashok ;

Manikandan, Venugopal ;

Devarajan, Nanjundappan .

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2011, 27 (05) :673-678

[10]

Maltabas Samed, 2013, VLSI TEST S VTS 2013, P1

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