Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

被引：62
|
作者：
Pant, P [1 ]
Roy, RK
Chatterjee, A
机构：
[1] Compaq Comp Corp, Shrewsbury, MA 01545 USA
[2] Mobilian Corp, Hillsboro, OR USA
[3] Georgia Inst Technol, Atlanta, GA 30332 USA
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2001年 / 9卷 / 02期
基金：
美国国家科学基金会;
关键词：
D O I：
10.1109/92.924061
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal-oxide-semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of a circuit by as much as 50%.
引用
收藏
页码：390 / 394
页数：5
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