Experimental Verification of Timing Measurement Circuit With Self-Calibration

被引：0

作者：

Chujo, Takeshi ^{[1
]}

Hirabayashi, Daiki ^{[1
]}

Li, Congbing ^{[1
]}

Kobayashi, Yutaro ^{[1
]}

Wang, Junshan ^{[1
]}

Kobayashi, Haruo ^{[1
]}

Katoh, Kentaroh ^{[2
]}

Koshi, Sato ^{[3
]}

机构：

[1] Gunma Univ, Div Elect & Informat, Kiryu, Gunma 3768516, Japan

[2] Tsuruoka Natl Coll Technol, Tsuruoka, Yamagata 9978511, Japan

[3] Hikari Sci, Tokyo 3660801, Japan

来源：

2014 19TH INTERNATIONAL MIXED-SIGNALS, SENSORS AND SYSTEMS TEST WORKSHOP (IMS3TW) | 2014年

关键词：

Time-to-Digital Converter; Time Measurement; Self-Calibration; Histogram Method; FPGA;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper describes the architecture, implementation and measurement results for a Time-to-Digital Converter (TDC), with histogram-method self-calibration, for high-speed I/O interface circuit test applications. We have implemented the proposed TDC using a Programmable System-on-Chip (PSoC), and measurement results show that TDC linearity is improved by the self-calibration. All TDC circuits, as well as the self-calibration circuits can be implemented as digital circuits, even by using FPGA instead of full custom ICs, so this is ideal for fine CMOS implementation with short design time.

引用

页数：6

共 9 条

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[2] [Anonymous], 2006, ALL DIGITAL FREQUENC
[3] [Anonymous], 2010, IEEE AS PAC C CIRC S
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[5] Katoh K., 2013, IEEE AS TEST S YIL T
[6] Kobayashi H, 2003, IEICE T FUND ELECTR, VE86A, P504
[7] Komuro T., 2007, Transactions of the Institute of Electronics, Information and Communication Engineers C, VJ90C, P125
[8] Rivoir J, 2006, INT TEST CONF P, P198
[9] Multi-bit Sigma-Delta TDC Architecture with Improved Linearity
Uemori, Satoshi
Ishii, Masamichi
Kobayashi, Haruo
Hirabayashi, Daiki
Arakawa, Yuta
Doi, Yuta
Kobayashi, Osamu
Matsuura, Tatsuji
Niitsu, Kiichi
Yano, Yuji
Gake, Tatsuhiro
Yamaguchi, Takahiro J.
Takai, Nobukazu
[J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2013, 29 (06): : 879 - 892

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