On-chip interconnect trends, challenges and solutions: how to keep RC and reliability under control

被引：0

作者：

Tokei, Zs. ^{[1
]}

Ciofi, I. ^{[1
]}

Roussel, Ph. ^{[1
]}

Debacker, P. ^{[1
]}

Raghavan, P. ^{[1
]}

van der Veen, M. H. ^{[1
]}

Jourdan, N. ^{[1
]}

Wilson, C. J. ^{[1
]}

Gonzalez, V. V. ^{[1
]}

Adelmann, C. ^{[1
]}

Wen, L. ^{[1
]}

Croes, K. ^{[1
]}

Moors, O. Varela Pedreira K. ^{[1
]}

Krishtab, M. ^{[1
]}

Armini, S. ^{[1
]}

Bommels, J. ^{[1
]}

机构：

[1] Imec, Kapeldreef 75, B-3001 Leuven, Belgium

来源：

2016 IEEE SYMPOSIUM ON VLSI TECHNOLOGY | 2016年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Interconnects pose increasing challenges as technology scaling proceeds. In order to overcome these challenges simultaneous optimization of novel metallization schemes, new materials, circuit and system level approaches are required.

引用

页数：2

共 42 条

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