System level design and power analysis of architectures for SATD calculus in the H.264/AVC

The new generation of video coding standards (H.264/MPEG Advanced Video Codec) addresses the requirements of a network-friendly and scalable video representation, and increasing by a factor of two the compression efficiency of the current technology. The H.264 uses the SATD metric for the calculus of the prediction error. The SATD procedure may be called about I million times during the visualization of a 352x288 pixel video sequence of 10 seconds. Therefore the accurate design of a dedicated hardware for the SATD is relevant in the performance of the complete codec. This paper presents four architectures described in SystemC for the VLSI implementation of the calculus of the SATD metric. The performances of the architectures in terms of signal to noise ratio and power dissipation have been evaluated using a new SystemC library developed by the authors for the estimation of power consumption in a SystemC description of the architecture. Comparisons have been performed for different values of the number of bits of the internal representation for the four architectures. Four standard video sequences (Akiyo, Stefan, Mobile&calendar, Container) have been used to test the performance of the architectures.