Impact of gate dielectric on overall electrical performance of Quadruple gate FinFET

Due to better scalability and more immunity to short channel effects in recent technology nodes, Quadruple gate FinFET is introduced as a potential candidate among multiple gate FET devices. This article presents an investigation of the impact of gate dielectric constant on DC electrical parameters in Quadruple gate FinFET. Drive current (I-ds), leakage current (I-off), current switching ratio (I-on /I-off), sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are observed by varying gate dielectric constant. Additionally, the influence of the gate dielectric on analog/RF performance parameters in terms of transconductance (g(m)), output conductance (g(d)), intrinsic gain (g(m)/g(d)), gate capacitance (C-gg) cutoff frequency (f(t)), and intrinsic delay are reported with the help of a commercial two-dimensional device simulator. Along variation of gate dielectric constant, some linear parameters such as g(m2), g(m3), VIP2 are also analyzed for wireless communication. For high-k dielectric, due to enhancement of oxide capacitance, we observed an increase in drive current, transconductance, switching ratio, and gate capacitance. Linearity parameters are also strongly affected by operating gate dielectric.