Design of unique Four-Bit/Cell polycrystalline silicon-oxide-silicon nitride-oxide-silicon devices utilizing vertical channel of silicon pillar

被引：1

作者：

Mun, Kyung Sik ^{[1
]}

Kim, Jae-Ho ^{[1
]}

Kim, Tae Whan ^{[1
]}

Dal Kwack, Kae ^{[1
]}

机构：

[1] Hanyang Univ, Div Elect & Comp Engn, Adv Semicond Res Ctr, Seoul 133791, South Korea

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS | 2007年 / 46卷 / 11期

关键词：

SONOS; ONO; NAND flash memory; program disturbance; pass disturbance; self-boosting program-inhibiting scheme; program-inhibited cell;

D O I：

10.1143/JJAP.46.7237

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

Unique four-bit/cell polycrystalline silicon-oxide-silicon nitride-oxide-silicon (SONOS) devices with separated ONOs utilizing the vertical channel of a silicon pillar, denoted as silicon pillar vertical-channel SONOS (SPVC-SONOS) devices, were designed to increase memory density. A narrow charge distribution and improved data retention were achieved owing to the separation of the storage nitride layers. An analytical model of the transient characteristics for investigating the effects of the dielectric composition and the erase speed, which was dependent on the erase voltage, was developed. Floating nodes acting as a trap site were added in the nitride layer to simulate the program characteristics using the conventional device simulator MEDICI. The channel hot-electron-injection program, Fowler-Nordheim tunneling erase, and reverse mode read characteristics were estimated to verify the operation of the novel four-bit/cell SPVC-SONOS devices. The proposed unique four-bit/cell SPVC-SONOS devices can be used to increase memory density.

引用

页码：7237 / 7240

页数：4