Calibrating power supply signal measurements for process and probe card variations

被引：3

作者：

Acharyya, D ^{[1
]}

Plusquellic, J ^{[1
]}

机构：

[1] Univ Maryland Baltimore Cty, Dept CSEE, Baltimore, MD 21228 USA

来源：

DBT 2004: PROCEEDINGS OF THE 2004 IEEE INTERNATIONAL WORKSHOP ON CURRENT & DEFECT BASED TESTING | 2004年

关键词：

D O I：

10.1109/DBT.2004.1408948

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The power supply transient signal (I-DDT) methods that we propose for defect detection and localization analyze regional signal variations introduced by defects at a set of the power supply ports on the chip under test (CUT). A significant detractor to the successful application of such methods is dealing with the signal variations introduced by process and probe card parameter variations. In this paper we describe several calibration techniques designed to reduce the impact of these types of "non-defect" related chip and testing environment variations on the defect detection sensitivity of I-DDT testing methods. More specifically calibration methods are proposed that calibrate for signal variations introduced by performance differences and by changes in the probe card PLC parameters. The calibration methodology is demonstrated through SPICE simulations and in hardware.

引用

页码：23 / 30

页数：8

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