Reducing Inter-Application Interferences in Integrated CPU-GPU Heterogeneous Architecture

被引:0
作者
Wen, Hao [1 ]
Zhang, Wei [1 ]
机构
[1] Virginia Commonwealth Univ, Dept Elect & Comp Engn, Med Coll Virginia Campus, Richmond, VA 23284 USA
来源
2018 IEEE 36TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD) | 2018年
关键词
D O I
10.1109/ICCD.2018.00050
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Current heterogeneous CPU-GPU architectures integrate general purpose CPUs and highly thread-level parallelized GPUs (Graphic Processing Units) in the same die. The contention in shared resources between CPU and GPU, such as the last level cache (LLC), interconnection network and DRAM, may degrade both CPU and GPU performance. Our experimental results show that GPU applications tend to have much more power than CPU applications to compete for the shared resources in LLC and on-chip network, and therefore make CPU suffer from more performance loss. To reduce the GPU's negative impact on CPU performance, we propose a simple yet effective method based on probability to control the LLC replacement policy for reducing the CPU's inter-core conflict misses caused by GPU without significantly impacting GPU performance. In addition, we develop two strategies to combine the probability based method for the LLC and an existing technique called virtual channel partition (VCP) for the interconnection network to further improve the CPU performance. The first strategy statically uses an empirically pre-determined probability value associated with VCP, which can improve the CPU performance by 26% on average, but degrades GPU performance by 5%. The second strategy uses a sampling method to monitor the network congestion and dynamically adjust the probability value used, which can improve the CPU performance by 24%, and only have 1 or 2% performance overhead on GPU applications.
引用
收藏
页码:278 / 281
页数:4
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