Ultra low power ASIP design for wireless sensor nodes

被引：4

作者：

De Nil, Michael ^{[1
,2
]}

Yseboodt, Lennart ^{[1
]}

Bouwens, Frank ^{[2
]}

Hulzink, Jos ^{[2
]}

Berekovic, Mladen ^{[2
,5
]}

Huisken, Jos ^{[3
]}

Van Meerbergen, Jef ^{[1
,4
]}

机构：

[1] Eindhoven Univ Technol, POB 513, NL-5600 MB Eindhoven, Netherlands

[2] IMEC NL, Leuven, Belgium

[3] Silicon Hive, Eindhoven, Netherlands

[4] Philips Res, Amsterdam, Netherlands

[5] Delft Univ Technol, Delft, Netherlands

来源：

2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4 | 2007年

关键词：

D O I：

10.1109/ICECS.2007.4511249

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents a methodology for designing an ultra low power application specific instruction set processor. This paper shows the different steps to develop a digital signal processing architecture for a single channel ECG application assuming a system level power dissipation constraint of 100 mu W. We follow a bottleneck driven approach based on the following steps. First coarse grained clock gating is applied. Next, the static as well as the dynamic dissipation of the digital processor is reduced and possibilities for future improvements are discussed. Finally, an optimal processor is built consuming 8.40 mu W when running the reference application.

引用

页码：1352 / +

页数：2