Efficient One-Step Decodable Limited Magnitude Error Correcting Codes for Multilevel Cell Main Memories

As technology scales further, dynamic random-access memory (DRAM) scaling faces numerous challenges. Emerging non-volatile main memories (e.g., phase change memories) provide an attractive solution to the challenges faced by DRAM scaling due to their high density and low cost. But phase change memories suffer from the problem of resistance drifts, which are of limited magnitude and causes read reliability degradation. For single error correction, Hamming codes and beyond single-error correction, Orthogonal Latin Square codes have been used due to their one-step decoding procedure. But with the limited magnitude error model, these codes are inefficient since they incur considerable redundancy. This paper proposes a new systematic limited magnitude error correcting non-binary Hamming code for a single-error correction specifically to address limited magnitude errors in multilevel cell memories storing multiple bits per cell. For memory architectures involving multiple error correction, a new decimal arithmetic based Orthogonal Latin Square code is also proposed. A general construction methodology is presented to correct errors of limited magnitude and is compared to existing schemes addressing limited magnitude errors in phase change memories. For non-binary Hamming codes, it is shown that the proposed codes provide better latency and complexity compared to existing limited magnitude error correcting non-binary Hamming codes as well as better redundancy compared to the symbol extended version of binary Hamming codes. The proposed limited magnitude Orthogonal Latin Square codes are shown to achieve better redundancy and better area compared to existing schemes with the tradeoff of slight increase in decoding and encoding latency.