HM-Mesh: Energy Efficient Hybrid Multiple Network-on-Chip

With the development of multiple processors SoC (system on chip), there are more and more challenges to the design of NoC (network-on-chip), one of which is to design energy-efficient NoC architecture, due to its large power consumption. Multi-NoC (multiple network-on-chip) has been proposed to save leakage power for its advantages in power gating network components. In this paper, we propose a hybrid Multi-NoC design, called HM-Mesh. HM-Mesh adopts a hybrid CMesh and Mesh architecture, and leverages CMesh network to respect its power efficiency at low network utilization. HM-Mesh is able to adaptively schedule packets to different subnets according to the network load, and smartly perform power gating to achieve good energy efficiency. The experimental results show that HMMesh delivers an average of 4.87% higher performance than Catnap, the state of the art power efficient Multi-NoC design. More importantly, HM-Mesh consumes an average of 29.2% less power than that of Catnap.