Effect of gate voltage on hot-carrier-induced on-resistance degradation in high-voltage n-type lateral diffused metal-oxide-semiconductor transistors

被引：3

作者：

Chen, Shiang-Yu ^{[1
]}

Chen, Jone F. ^{[1
]}

Wu, Kuo-Ming ^{[2
]}

Lee, J. R. ^{[1
]}

Liu, C. A. ^{[2
]}

Hsu, S. L. ^{[2
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, Inst Microelect, Tainan 701, Taiwan

[2] Taiwan Semicond Mfg Co, Hsinchu 300, Taiwan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2008年 / 47卷 / 04期

关键词：

LDMOS; high voltage; hot carrier; reliability;

D O I：

10.1143/JJAP.47.2645

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

The phenomenon and mechanism of hot-carrier-induced on-resistance (R-on) degradation for the n-type lateral diffused metal-oxide-semiconductor (MOS) transistors stressed under various gate voltages (V-g) are investigated. R-on degradation of the device is found to be attributed to the interface state (N-it) generation in the N- drift region. Moreover, R-on degradation is almost identical for the devices stressed under medium V-g and high V-g, despite the fact that bulk current of the device is much greater at high V-g bias. Such an anomalous R-on degradation is suggested to be the result of two combined factors: the magnitude of impact ionization rate and N-it generation efficiency.

引用

页码：2645 / 2649

页数：5

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