High-Throughput and Low-Power Integrated Direct/Inverse HEVC Quantization Hardware Design

被引：2
|
作者：
Braatz, Luciano [1 ]
Zatt, Bruno [1 ]
Palomino, Daniel [1 ]
Agostini, Luciano [1 ]
Porto, Marcelo [1 ]
机构：
[1] Fed Univ Pelotas UFPel, Grp Architectures & Integrated Circuits GACI, Video Technol Res Grp ViTech, Pelotas, Brazil
来源：
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2018年
关键词：
HEVC; Video coding; Quantization; Hardware architecture;
D O I：
10.1109/ISCAS.2018.8351183
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a high-throughput and low-power integrated HEVC direct/inverse quantization hardware design. The main focus of this design is to allow the evaluation of multiple coding modes during the residual encoding process of the HEVC for real-time Ultra-High Definition (UHD) video processing. The ASIC synthesis results, for a Nangate 45nm standard cell library, presented a maximum operational frequency of 1679.51MHz and a processing rate of 53.74 Gsps (giga samples per second). This throughput allows processing of real-time up to 72 coding modes for UHD 4K@60fps or up to nine coding modes for the UHD 8K@120fps while dissipating 369.37mW.
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页数：5
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