An FPGA-based High-Throughput Stream Join Architecture

被引：4

作者：

Kritikakis, Charalabos ^{[1
]}

Chrysos, Grigorios ^{[1
]}

Dollas, Apostolos ^{[1
]}

Pnevmatikatos, Dionisios N. ^{[1
]}

机构：

[1] Tech Univ Crete, Microprocessor & Hardware Lab, Khania, Greece

来源：

2016 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL) | 2016年

关键词：

stream processing; ScaleJoin; join operator; FPGA architecture; WINDOW JOINS;

D O I：

10.1109/FPL.2016.7577354

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Stream join is a fundamental operation that combines information from different high-speed and high-volume data streams. This paper presents an FPGA-based architecture that maps the most performance-efficient stream join algorithm, i.e. ScaleJoin, to reconfigurable logic. The system was fully implemented on a Convey HC-2ex hybrid computer and the experimental performance evaluation shows that the proposed system outperforms by up to one order of magnitude the corresponding fully optimized parallel software-based solution running on a high-end 48-core multiprocessor platform. The proposed architecture can be used as a generic template for mapping stream processing algorithms to reconfigurable logic, taking into consideration real-world challenges.

引用

页数：4

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