Field Programmable Logic Arrays Implementation of Scene-Based Nonuniformity Correction Algorithm

被引:1
作者
Njuguna, Josphat Chege [1 ]
Alabay, Emre [1 ]
Celebi, Anil [1 ]
机构
[1] Kocaeli Univ, Elect & Commun Engn, Kocaeli, Turkey
来源
2021 8TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND ELECTRONICS ENGINEERING (ICEEE 2021) | 2021年
关键词
FPGA; fixed pattern noise; high-level synthesis; IRFPA; nonuniformity; SBNUC;
D O I
10.1109/ICEEE52452.2021.9415961
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, the implementation of scene-based nonuniformity correction (SBNUC) algorithm is presented based on field programmable logic arrays (FPGA) for infrared focal plane arrays (IRFPA). An efficient hardware architecture for the proposed algorithm is presented. The architecture is modeled using C++ in the High-level Synthesis (HLS) tool. Furthermore, it is implemented on an FPGA device fabricated at a 16nm technology node. According to experimental results, low resource utilization, low power consumption, and a maximum frequency of 300MHz are achieved. The simulation and MATLAB results are compared to test the accuracy in which there are close similarities.
引用
收藏
页码:6 / 9
页数:4
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