Optimal parameters for ΔΣ modulator topologies

被引：115

作者：

Marques, A ^{[1
]}

Peluso, V ^{[1
]}

Steyaert, MS ^{[1
]}

Sansen, WM ^{[1
]}

机构：

[1] Katholieke Univ Leuven, ESAT, B-3001 Heverlee, Belgium

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1998年 / 45卷 / 09期

关键词：

ADC; analog-to-digital; data converter; delta-sigma; noise-shaping;

D O I：

10.1109/82.718590

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A systematic study of single-loop, cascaded, and multibit Delta Sigma modulators of second to fourth order is presented, based on a combination of behavioral simulations and linear modeling. Constraints for optimal performance and precise guidelines for the choice of parameters are derived. Moreover, the optimal parameters and the corresponding performance are found and given in tables. A graph showing the maximal achievable performance of each topology as a function of the oversampling ratio is presented, offering a valuable help for the design of analog-to-digital converters.

引用

页码：1232 / 1241

页数：10

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