Low-voltage low-power accurate CMOS VT extractor

被引:16
作者
Fikos, G [1 ]
Siskos, S [1 ]
机构
[1] Univ Thessaloniki, Dept Phys, GR-54006 Thessaloniki, Greece
关键词
analog VLSI; CMOS; low-power circuits; low-voltage circuits; V-T extractors;
D O I
10.1109/82.943334
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Circuits extracting a MOSFET's threshold voltage belong to the general category of bias circuits. Since these circuits do not process signal inputs, their power consumption should be low, while preserving high accuracy and robustness of the output against supply voltage variations and transistor mismatch. In this brief, a low-voltage low-power self-biased analog CMOS VT extractor is proposed. By utilizing novel feedback on a simple low-voltage VT extracting block, the extractor presents less than 0.3% error for wide supply voltage range, and achieves low-power consumption and self-compensation for second-order effects and mismatch. These features are supported by simulation results.
引用
收藏
页码:626 / 628
页数:3
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