High Volume Electrical Characterization of Semiconductor Qubits

被引：21

作者：

Pillarisetty, R. ^{[1
]}

George, H. C. ^{[1
]}

Watson, T. F. ^{[1
]}

Lampert, L. ^{[1
]}

Thomas, N. ^{[1
]}

Bojarski, S. ^{[1
]}

Amin, P. ^{[1
]}

Caudillo, R. ^{[1
]}

Henry, E. ^{[1
]}

Kashani, N. ^{[1
]}

Keys, P. ^{[1
]}

Kotlyar, R. ^{[1
]}

Luthi, F. ^{[1
]}

Michalak, D. ^{[1
]}

Millard, K. ^{[1
]}

Roberts, J. ^{[1
]}

Torres, J. ^{[1
]}

Zietz, O. ^{[1
]}

Krahenmann, T. ^{[2
]}

Zwerver, A. -M. ^{[2
]}

Veldhorst, M. ^{[2
]}

Scappucci, G. ^{[2
]}

Vandersypen, L. M. K. ^{[2
]}

Clarke, J. S. ^{[1
]}

机构：

[1] Intel Corp, Technol & Mfg Grp, Hillsboro, OR 97124 USA

[2] Delft Univ Technol, QuTech & Kavli Inst Nanosci, POB 5046, NL-2600 GA Delft, Netherlands

来源：

2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2019年

关键词：

D O I：

10.1109/iedm19573.2019.8993587

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Perhaps the greatest challenge facing quantum computing hardware development is the lack of a high throughput electrical characterization infrastructure at the cryogenic temperatures required for qubit measurements. In this article, we discuss our efforts to develop such a line to guide 300mm spin qubit process development. This includes (i) working with our supply chain to create the required cryogenic high volume testing ecosystem, (ii) driving full wafer cryogenic testing for both transistor and quantum dot statistics, and (iii) utilizing this line to develop a quantum dot process resulting in key electrical data comparable to that from leading devices in literature, but with unprecedented yield and reproducibility.

引用

页数：4

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