An Improved Implementation Scheme for AVS Entropy Decoding Based on FPGA

被引：0

作者：

Zhu, Wen-Ge ^{[1
]}

Yi, Qing-Ming ^{[1
]}

Li, Wei-Dan ^{[1
]}

机构：

[1] Act Jinan Univ, Integrated Circuit Design Joint Lab Guangzhou, Coll Informat Sci & Technol, Guangzhou, Guangdong, Peoples R China

来源：

PROCEEDINGS OF THE 2011 INTERNATIONAL CONFERENCE ON INFORMATICS, CYBERNETICS, AND COMPUTER ENGINEERING (ICCE2011), VOL 2: INFORMATION SYSTEMS AND COMPUTER ENGINEERING | 2011年 / 111卷

关键词：

AVS; entropy decoding; barrel shifter; FPGA;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

An improved implementation scheme for AVS entropy decoding based on FPGA is proposed in this paper. The additional control circuit is used to get rid of the code streams parsed every cycle without adding any parsing periods. And it makes the barrel shifter prepositive so as to balance the time sequence path in the front end. In this way, the deficiency in the traditional structure of variable length decoding is conquered. Compared with the traditional structure, the proposed scheme achieves 43.2 percent time sequence improvement at the cost of 2.5 percent LE and the real-time high-definition (4:2:2) video decoding sequence can be implemented on Cyclone II EP2C35F672C6.

引用

页码：489 / 496

页数：8