Truly rapid prototyping requires high level synthesis

被引：3

作者：

Doncev, G ^{[1
]}

Leeser, M ^{[1
]}

Tarafdar, S ^{[1
]}

机构：

[1] Northeastern Univ, Dept Elect & Comp Engn, Boston, MA 02115 USA

来源：

NINTH INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING - PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/IWRSP.1998.676676

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Truly rapid prototyping requires a combination of abstract design tools and field programmable logic. In this paper we study the application of high-level synthesis (HLS) in the design of field-programmable gate array (FPGA) based systems. Our experience, using Synopsys Behavioral Compiler to map designs onto the Altera RIPP10 board, shows that HLS allows for a level of design space exploration unrealizable with register transfer level techniques. In addition, the use of HLS tools allows designers to prototype their designs with high quality results and much faster design turn around times. We discuss these issues in the context of our experiences with mapping a DTMF receiver onto the RIPP10 board.

引用

页码：101 / 106

页数：6