64-bit carry-select adder with reduced area

被引：63
作者：
Kim, Y [1 ]
Kim, LS [1 ]
机构：
[1] Korea Adv Inst Sci & Technol, Dept Elect Engn, Yusong Gu, Taejon, South Korea
来源：
ELECTRONICS LETTERS | 2001年 / 37卷 / 10期
关键词：
D O I：
10.1049/el:20010430
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A carry-select adder can be implemented by using a single ripple-carry adder and an add-one circuit instead of using dual ripple-carry adders. A multiplexer-based add-one circuit is proposed to reduce the area with negligible speed penalty. The proposed 64 bit carry-select adder requires 42% fewer transistors than the conventional carry-select adder.
引用
收藏
页码：614 / 615
页数：2
相关论文
共 50 条
  • [31] Power and area-optimised Carry-Select Adder architecture for standard cell-based design
    Shanmugam, Muthukumar
    Choi, GoangSeog
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2015, 102 (08) : 1348 - 1360
  • [32] 64-bit pipeline carry lookahead adder using all-N-transistor TSPC logics
    Cheng, KH
    Cheng, SW
    Lee, WS
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2006, 15 (01) : 13 - 27
  • [33] An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell
    You, Heng
    Yuan, Jia
    Tang, Weidi
    Qiao, Shushan
    ELECTRONICS, 2019, 8 (10)
  • [34] 16 Bit Power Efficient Carry Select Adder
    Gaur, Nidhi
    Mehra, Anu
    Kumar, Pradeep
    Kallakuri, Sankalp
    2019 6TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN), 2019, : 558 - 561
  • [35] Power and Area Efficient Carry Select Adder
    Anagha, U. P.
    Pramod, P.
    PROCEEDINGS OF THE 2015 IEEE RECENT ADVANCES IN INTELLIGENT COMPUTATIONAL SYSTEMS (RAICS), 2015, : 17 - 20
  • [36] 64-bit hybrid dual-threshold voltage power-aware conditional carry adder design
    Cheng, KH
    Cheng, SW
    Huang, CW
    4TH IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2004, : 65 - 68
  • [37] 480ps 64-bit Race Logic adder
    Lee, SJ
    Woo, R
    Yoo, HJ
    2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2001, : 27 - 28
  • [38] 64-bit reconfigurable adder for low power media processing
    Perri, S
    Corsonello, P
    Cocorullo, G
    ELECTRONICS LETTERS, 2002, 38 (09) : 397 - 399
  • [39] A 64-bit fast adder with 0.18μm CMOS technology
    Jin, ZP
    Shen, XB
    Bai, YQ
    International Symposium on Communications and Information Technologies 2005, Vols 1 and 2, Proceedings, 2005, : 1167 - 1171
  • [40] A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder
    Hasan, Mehedi
    Hossain, Muhammad Saddam
    Siddique, Abdul Hasib
    Hossain, Mainul
    Zaman, Hasan U.
    Islam, Sharnali
    MICROELECTRONICS JOURNAL, 2021, 109
12345