64-bit carry-select adder with reduced area

被引：63
|
作者：
Kim, Y [1 ]
Kim, LS [1 ]
机构：
[1] Korea Adv Inst Sci & Technol, Dept Elect Engn, Yusong Gu, Taejon, South Korea
来源：
ELECTRONICS LETTERS | 2001年 / 37卷 / 10期
关键词：
D O I：
10.1049/el:20010430
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A carry-select adder can be implemented by using a single ripple-carry adder and an add-one circuit instead of using dual ripple-carry adders. A multiplexer-based add-one circuit is proposed to reduce the area with negligible speed penalty. The proposed 64 bit carry-select adder requires 42% fewer transistors than the conventional carry-select adder.
引用
收藏
页码：614 / 615
页数：2
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