Design Space Exploration of RISC Architectures Using Retargetability

被引：0

作者：

Arora, Harsh ^{[1
]}

Gupta, Abhinav ^{[2
]}

Singhai, Raunak ^{[3
]}

Purwar, Diptanshu ^{[4
]}

机构：

[1] VIT Univ, Sch Comp Sci & Engn, Vellore, Tamil Nadu, India

[2] Capital Float, Software R&D, Bangalore, Karnataka, India

[3] SAP Labs, Software Div, Madras, Tamil Nadu, India

[4] Samsung Elect, Mobile Comp Div, Noida, India

来源：

2015 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS (VLSI-SATA) | 2015年

关键词：

Design Space Exploration; RISC Architecture; Retargetability; Architecture Description Language;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Processor development is done in stages. It is a safe bet if we start by modeling the processor at a high level of abstraction, perform refinements at high level, and when we are satisfied by the performance, go into manufacturing. The process of refinement is done by evaluating the design criteria. This process generally goes through a cycle that can be described as Design Space Exploration (DSE). In this paper, we describe how to model a processor in an Architecture Description Language (ADL), how to generate tools to perform DSE, and finally how to evaluate performance.

引用

页数：3

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