Asynchronous logic design - from concepts to implementation

被引：0

作者：

Delvai, Martin ^{[1
]}

Steininger, Andreas ^{[1
]}

机构：

[1] Vienna Univ Technol, Inst Comp Engn, A-1040 Vienna, Austria

来源：

3RD INT CONF ON CYBERNETICS AND INFORMATION TECHNOLOGIES, SYSTEMS, AND APPLICAT/4TH INT CONF ON COMPUTING, COMMUNICATIONS AND CONTROL TECHNOLOGIES, VOL 1 | 2006年

关键词：

asynchronous logic; delay insensitive design; asynchronous processor micro-pipeline;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The large body of literature on asynchronous logic spans from theoretical concept papers to ASIC implementation reports. There is, however a considerable gap in between that we are addressing in this paper Starting from the basic concept of a methodology called Four State Logic (FSL) we show step by step how an FSL circuit can he implemented using standard gates. In order to facilitate efficient practical investigations of asynchronous design we propose an FPGA as a target platform and report our experiences.

引用

页码：81 / 86

页数：6

共 15 条

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