Integration of Ferroelectric HfxZr1-xO2 on Vertical III-V Nanowire Gate-All-Around FETs on Silicon

被引：18

作者：

Persson, Anton E. O. ^{[1
]}

Zhu, Zhongyunshen ^{[1
]}

Athle, Robin ^{[2
]}

Wernersson, Lars-Erik ^{[1
]}

机构：

[1] Lund Univ, Dept Elect & Informat Technol, S-22100 Lund, Sweden

[2] Lund Univ, Dept Elect & Informat Technol & NanoLund, S-22100 Lund, Sweden

来源：

IEEE ELECTRON DEVICE LETTERS | 2022年 / 43卷 / 06期

基金：

瑞典研究理事会; 欧洲研究理事会;

关键词：

Logic gates; Silicon; FeFETs; Nanoscale devices; Switches; Temperature measurement; MOSFET; Ferroelectrics; ferroelectric field effect transistor (FeFET); gate-all-around MOSFET; hafnium zirconium oxide; InAs; vertical nanowire; TRANSISTORS;

D O I：

10.1109/LED.2022.3171597

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs.

引用

页码：854 / 857

页数：4

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