FPGA Implementation of Symmetric Systolic FIR Filter using Multi-channel Technique

High performance Finite Impulse Response (FIR) filters are extensively used in digital signal processing (DSP), communications, image processing and many more areas. This paper approaches Field Programmable Gate Arrays (FPGAs) based on systolic FIR architectures using multi-channel technique with symmetric coefficients to ensure faster response and optimum area. The embedded Digital Signal Processing (DSP) blocks for its multiply-accumulator (MAC) perform accurate operations where the filter architecture is efficiently realized in the reconfigurable hardware platform. The characteristics of systolic FIR architecture are synchrony, modularity and regularity to make a perfect filter design. Also its pipeline structure provides high throughput and symmetric technique reduces the memory size. Both of these techniques improve the overall performance of the FIR architecture in FPGA domain. The proposed FIR architecture has been successfully verified by Xilinx ISE 14.7 tool and then implemented on Virtex-5 FPGA board. The design method shows a great improvement of maximum operating frequency and save the area as compared to the earlier architectures.