[1] Univ Cincinnati, Dept ECECS, Cincinnati, OH 45221 USA
来源:
NINTH INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING - PROCEEDINGS
|
1998年
关键词:
D O I:
10.1109/IWRSP.1998.676695
中图分类号:
TP3 [计算技术、计算机技术];
学科分类号:
0812 ;
摘要:
Performance evaluation is essential for tradeoff analysis during rapid prototyping. Existing performance evaluation strategies based on co-simulation and static analyses are either too slow or error prone. We therefore present an intermediate approach based on profiling and scheduling for rapid prototyping of hardware-software codesigns. Our performance evaluation tool obtains representative task timings by profiling which is done simultaneously with system specification. During design space exploration the tool obtains performance estimates by using well known scheduling and novel re-timing heuristics. It is capable of obtaining both non-pipelined and pipelined schedules. The tool includes an area estimator which calculates the amount of hardware area required by the design by taking resource sharing between different hardware tasks in to account. The tool also allows the user to evaluate the performance of a particular schedule with different task timings. In contrast to co-simulation and static analysis, the tool is able to provide fast and accurate performance estimates. The effectiveness of the tool in a rapid-prototyping environment is demonstrated by a case study.