An Ultra-Wideband Fast Frequency Ramp Synthesizer at 60 GHz With Low Noise Using a New Loop Gain Compensation Technique

Phase-locked loops (PLLs) for ultra-wideband, low noise, and linear frequency ramp synthesis exhibit a wide variation of the loop gain, if no compensation method is applied. This impairs the performance of the PIA, and the corresponding microwave measurement systems. To overcome the disadvantages of existing compensation techniques, we present a new compensation method based on a phase-frequency detector gain modulation. This offers low hardware complexity and avoids additional noise. Furthermore, we present an ultra-wideband, low noise monolithic microwave-integrated circuit for 60-GHz PLLs. Based on this, a 60-GHz frequency synthesizer with a modulation bandwidth of 22 GHz and a jitter of less than 79 fs at the center frequency are realized. The new compensation technique reduces the variation of the loop gain from 14.2:1 to 1.67:1 and is compared with an existing compensation technique utilizing a voltage-dependent clamping network, which reduces the variation of the loop gain to 1.78:1. Due to the reduction of the variation of the loop gain, the maximum ramp slope increases from 22 GHz/2.9 ms up to 22 GHz/0.35 ms. In addition, the time jitter of the output signal of the PLL decreases by up to 18%. Furthermore, the PLL performance is constant in the temperature range from 0 degrees C to 70 degrees C.