Routing Algorithms for NoC Architecture a Relative Analysis

被引:2
作者
Sayankar, Bharati B. [1 ]
Agrawal, Pankaj [2 ]
Dorle, S. S. [3 ]
机构
[1] GHRCE, Nagpur, Maharashtra, India
[2] RCOEM, Nagpur, Maharashtra, India
[3] GHRCE, Dept Elect, Nagpur, Maharashtra, India
来源
2013 SIXTH INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING AND TECHNOLOGY (ICETET 2013) | 2013年
关键词
NoC architecture; Switching technique; Wormhole Routing algorithm and Virtual Cut through (VCT);
D O I
10.1109/ICETET.2013.29
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
To make the interconnection inside a System on Chip (SoC) Network on C hi p (NoC) is a new paradigm. The Network-on-Chip (NOC) have many advantages on traditional bus based System-on-Chip (SoC). In past the interconnections are based on a bus structure. But the bus based structure does not meet the needs of the recent advanced technology. In many complicated network the bus structure blocks the traffic. In NoC technology the bus structure is replaced with a network which is similar to the Internet. Generally Segments communicate with each other by transferring packetized data over the network. Just like a computer network the NoC network consists of devices that use the network and routers that direct the traffic between devices and wires that connect devices to routers and routers to other routers. The network topology and a routing algorithm a re the essential things in the network design of the NoC. Routers route the packets based on the algorithm that they use. The different systems choose the different algorithms. Each and every system has its own requirements for the routing algorithm. This paper presents the relative analysis on the basics of networking on Network on Chip systems. Also presents the comparative analysis and implementation of Wormhole and Virtual Cut-through router. The simulation of Wormhole system and VCT is done in Modelsim SE as a simulation debugging tool.
引用
收藏
页码:105 / 106
页数:2
相关论文
共 9 条
[1]  
Agarwal A., 2009, CONTRIBUTIONS J ENG, V3
[2]  
Kumar A., 2004, Communication networking: an analytical approach
[3]  
Pande P. P., 2005, PERFORMANCE EVALUATI
[4]   Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip [J].
Rijpkema, E ;
Goossens, K ;
Radulescu, A ;
Dielissen, J ;
van Meerbergen, J ;
Wielage, P ;
Waterlander, E .
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2003, 150 (05) :294-302
[5]  
Sadawarte Y. A., COMP STUDY SWITCHING
[6]  
Sadawarte Y.A., 2010, INT J COMPUTER ENG I, V17, P52
[7]  
SALMINEN ET AL., 2008, Survey of network-on-chip proposals
[8]  
Taghavi T., 2006, P IEEE INT S CIRC SY
[9]  
Ye T.T., 2002, P DES AUT C