A Generalized Threshold Voltage Model of Tied and Untied Double-Gate Junctionless FETs for a Symmetric and Asymmetric Structure

被引：12
作者：
Hur, Jae [1 ]
Choi, Ji-Min [1 ]
Woo, Jong-Ho [1 ]
Jang, Hyunjae [1 ]
Choi, Yang-Kyu [1 ]
机构：
[1] Korea Adv Inst Sci & Technol, Dept Elect Engn, Taejon 305701, South Korea
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2015年 / 62卷 / 09期
基金：
新加坡国家研究基金会;
关键词：
Asymmetric double-gate (DG); DG junctionless FET (DGJL-FET); generalized threshold voltage (V-T) model; symmetric DG; tied mode DG; untied mode DG; MOSFETS; TRANSISTORS;
D O I：
10.1109/TED.2015.2436415
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A general potential model is proposed for all types of double-gate junctionless FETs (DGJL-FETs), i.e., the symmetric versus asymmetric DG structures and the tied versus untied DG structures. The potential model is obtained with a simple form through a 2-D Poisson's equation based on the assumption that the vertical channel potential is approximated to a cubic function of the position in order to consider all types of DGJL-FETs. An analytical threshold voltage (VT) equation via the potential model is derived with the gate voltage when the sum of the depletion widths from the front-gate and the back-gate equals the body thickness. The analytic solution of VT shows good agreement with the simulation results down to a channel length <20 nm. The variability of VT is analyzed for various device parameters. The back-gate effect of the untied DG structure is also investigated.
引用
收藏
页码：2710 / 2716
页数：7
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