The Hysteretic Ferroelectric Tunnel FET

被引：41

作者：

Ionescu, Adrian M. ^{[1
]}

Lattanzio, Livio ^{[1
]}

Salvatore, Giovanni A. ^{[1
]}

De Michielis, Luca ^{[1
]}

Boucart, Kathy ^{[1
]}

Bouvet, Didier ^{[2
]}

机构：

[1] Ecole Polytech Fed Lausanne, Nanoelect Devices Lab, CH-1015 Lausanne, Switzerland

[2] Ecole Polytech Fed Lausanne, Ctr Micro & Nanotechnol, CH-1015 Lausanne, Switzerland

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2010年 / 57卷 / 12期

关键词：

Ferroelectric FET; memory; nanoelectronic switch; tunnel FET; THIN-FILMS; FIELD; TRANSISTORS; LIFETIMES; VOLTAGE; MODEL;

D O I：

10.1109/TED.2010.2079531

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present the fabrication and the electrical characterization of ferroelectric tunnel FETs (Fe-TFETs). This novel family of hysteretic switches combines the low subthreshold power of band-to-band tunneling devices with the retention characteristics of Fe gate stacks, offering some interesting features for future one-transistor (1T) memory cells. We report I-on/I-off larger than 10(5) and I-off on the order of 100 fA/mu m in micrometer-scale p-type Fe-TFETs fabricated on ultrathin-film (fully depleted) silicon-on-insulator substrates with a SiO2/Al2O3/PVDF gate stack processed at low temperature. The hysteretic characteristics of the TFETs with Fe gate stacks are revealed by static experiments, and the principle of the proposed device is further confirmed by 2-D calibrated numerical simulations. Low temperature measurements down to 77 K confirm the reduced sensitivity of the TFET subthreshold swing to temperature and distinguish them from fabricated reference Fe metal-oxide-semiconductor FETs. Finally, we investigate the potential of Fe-TFETs as 1T memory devices and find retention times on the order of a few minutes at room temperature.

引用

页码：3518 / 3524

页数：7

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