A Coarse Model for Estimation of Switching Noise Coupling in Lightly Doped Substrates

被引：0
作者：
Babic, Milan [1 ,2 ]
Krstic, Milo [2 ]
机构：
[1] BTU Cottbus Senftenberg, Pl Deutsch Einheit 1, Cottbus, Germany
[2] IHP, Frankfurt, Oder, Germany
来源：
2015 IEEE 18TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS 2015) | 2015年
关键词：
Switching noise; lightly doped substrate; modeling; estimation; EXPERIMENTAL-VERIFICATION; METHODOLOGY; GENERATION; CHIP;
D O I：
10.1109/DDECS.2015.27
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The objective of this paper is to propose a coarse model for coupling of switching noise through lightly doped substrates. This could be achieved by assuming a regular placement of substrate contacts in a digital aggressor. Additionally, an approximation of equal ground bounce in an entire digital aggressor is applied. The proposed model is aimed for use as an estimation before placement, i.e. before knowing the exact layout details. Consequently, this model could be utilized as a guideline for determining the optimal floorplanning of digital blocks with regards to substrate noise coupling to sensitive analog modules. Extraction code is written in MATLAB. Evaluation of the model has shown that reasonable accuracy of the estimation could be expected and that the proposed method could be used as a baseline for early exploration of substrate noise characteristics of the design.
引用
收藏
页码：217 / 222
页数：6
相关论文
共 11 条
  • [1] Aragones X., 1999, ANAL SOLUTIONS SWITC
  • [2] SWAN: High-level simulation methodology for digital substrate noise generation
    Badaroglu, M
    Van der Plas, G
    Wambacq, P
    Donnay, S
    Gielen, GGE
    De Man, HJ
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2006, 14 (01) : 23 - 33
  • [3] Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies
    Badaroglu, M
    Donnay, S
    De Man, HJ
    Zinzius, YA
    Gielen, GGE
    Sansen, W
    Fondén, T
    Signell, S
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (07) : 1250 - 1260
  • [4] Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits
    Badaroglu, M
    van Heijningen, M
    Gravot, V
    Compiet, J
    Donnay, S
    Gielen, GGE
    De Man, HJ
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (11) : 1383 - 1395
  • [5] Donnay Stephane, 2004, SUBSTRATE NOISE COUP
  • [6] GALS Design for On-Chip Ground Bounce Suppression
    Fan, Xin
    Krstic, Milos
    Wolf, Christoph
    Grass, Eckhard
    [J]. 17TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC 2011), 2011, : 43 - 52
  • [7] Jakushokas R, 2010, IEEE INT SYMP CIRC S, P2346, DOI 10.1109/ISCAS.2010.5537192
  • [8] Jakushokas Renatas, 2011, THESIS U ROCHESTER R
  • [9] CHIP SUBSTRATE RESISTANCE MODELING TECHNIQUE FOR INTEGRATED-CIRCUIT DESIGN
    JOHNSON, TA
    KNEPPER, RW
    MARCELLO, V
    WANG, W
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1984, 3 (02) : 126 - 134
  • [10] Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits
    Salman, Emre
    Jakushokas, Renatas
    Friedman, Eby G.
    Secareanu, Radu M.
    Hartin, Olin L.
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 17 (10) : 1405 - 1418
12