the Review of Cache Partitioning in Multi-core Processor

被引:0
作者
Li, Shuo [1 ,2 ]
Xu, Gaochao [1 ]
Dong, Yushuang [1 ]
Wu, Feng [3 ]
机构
[1] Jilin Univ, Sch Comp Sci & Technol, Changchun 130023, Peoples R China
[2] Informat Ctr, State Tax Office Jilin Prov, Changchun, Peoples R China
[3] Jilin Commun Polytech, Changchun, Peoples R China
来源
ADVANCED MEASUREMENT AND TEST, PARTS 1 AND 2 | 2010年 / 439-440卷
关键词
multi-core; Cache; IPC; miss rate monitor; Qos;
D O I
10.4028/www.scientific.net/KEM.439-440.1223
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
With the development of microelectronics technology, Chip Multi-Processor (CMP) or multi-core design has become a mainstream choice for major microprocessor vendors. But in a chip-multiprocessor with a shared cache structure, the competing accesses from different applications degrade the system performance, resulting in non-optimal performance and non-predicting executing time. Cache partitioning techniques can exclusively partition the shared cache among multiple competing applications. In this paper, we first introduce the problems caused by Cache pollution in multicore processor structure; then present the different methods of Cache partitioning in multicore processor structure --categorizing them based on the different metrics. And finally, we discuss some possible directions for future research in the area.
引用
收藏
页码:1223 / +
页数:4
相关论文
共 27 条
[1]  
CHANG JC, 2007, INT C SUP SEATTL WAS
[2]  
Denning Peter., 1968, RESOURCE ALLOCATION
[3]  
Dybdahl H, 2006, LECT NOTES COMPUT SC, V4297, P22
[4]  
Guang S, 2008, CHINESE J COMPUTERS, V31, P1938
[5]  
GUANG S, 2008, INT C CONV HYBR INF
[6]  
GUANG S, 2008, MICROELECTRONICS COM, V25, P91
[7]  
HSU LR, 2006, P 15 INT C PAR ARCH
[8]  
Iyer R., 2004, P 18 ACM INT C SUP I
[9]  
JAIN P, 2001, INT C COMP AID DES
[10]  
Kim S., 2004, INT C PAR ARCH COMP