Insights Into the Power-Off and Power-On Transient Performance of Power-Rail ESD Clamp Circuits

被引:3
作者
Lu, Guangyi [1 ]
Wang, Yuan [1 ]
Wang, Yize [1 ]
Zhang, Xing [1 ]
机构
[1] Peking Univ, Inst Microelect, Key Lab Microelect Device & Circuits, Beijing 100871, Peoples R China
关键词
Electrostatic discharge (ESD); ESD clamp circuit; transient response; soft failure; DESIGN;
D O I
10.1109/TDMR.2017.2737653
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The power-off and power-on transient performance of power-rail electrostatic discharge (ESD) clamp circuits is investigated in this paper. In order to serve this purpose, the transient performance of a timed shutoff power-rail ESD clamp circuit in a 65-nm CMOS process is characterized by a three-terminal test method. Based on the characterization results, several insights are summarized: it is found that the big-FET response time of the investigated circuit is dependent on the pulse peak voltage. Besides, the resistor-capacitor network is verified to be a slew-rate detector instead of a rise-time detector. Moreover, the different bigFET response mechanisms under various poweron disturbances are clarified. In addition, the validity of these insights for other designs is also discussed in this paper.
引用
收藏
页码:577 / 584
页数:8
相关论文
共 22 条
[1]   Area-Efficient ESD Clamp Circuit With a Capacitance-Boosting Technique to Minimize Standby Leakage Current [J].
Altolaguirre, Federico A. ;
Ker, Ming-Dou .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2015, 15 (02) :156-162
[2]  
[Anonymous], P IEEE C LAS EL SAN
[3]  
[Anonymous], 2009, CEL FAM TLP VF TLP E
[4]  
[Anonymous], 2012, EMC PART 4 4 TEST ME
[5]  
[Anonymous], P EOS ESD S
[6]  
[Anonymous], 2008, EMC PART 4 2 TEST ME
[7]   System efficient ESD design [J].
Gossner, H. ;
Duvvury, C. .
MICROELECTRONICS RELIABILITY, 2015, 55 (12) :2607-2613
[8]  
Industry Council on ESD Target Levels, 2010, 1 IND COUNC ESD TARG
[9]  
Junjun Li, 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), P179, DOI 10.1109/EOSESD.2006.5256781
[10]   Component-level measurement for transient-induced latch-up in CMOS ICs under system-level ESD considerations [J].
Ker, Ming-Dou ;
Hsu, Sheng-Fu .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2006, 6 (03) :461-472