Insights Into the Power-Off and Power-On Transient Performance of Power-Rail ESD Clamp Circuits

被引：3

作者：

Lu, Guangyi ^{[1
]}

Wang, Yuan ^{[1
]}

Wang, Yize ^{[1
]}

Zhang, Xing ^{[1
]}

机构：

[1] Peking Univ, Inst Microelect, Key Lab Microelect Device & Circuits, Beijing 100871, Peoples R China

来源：

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2017年 / 17卷 / 03期

关键词：

Electrostatic discharge (ESD); ESD clamp circuit; transient response; soft failure; DESIGN;

D O I：

10.1109/TDMR.2017.2737653

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The power-off and power-on transient performance of power-rail electrostatic discharge (ESD) clamp circuits is investigated in this paper. In order to serve this purpose, the transient performance of a timed shutoff power-rail ESD clamp circuit in a 65-nm CMOS process is characterized by a three-terminal test method. Based on the characterization results, several insights are summarized: it is found that the big-FET response time of the investigated circuit is dependent on the pulse peak voltage. Besides, the resistor-capacitor network is verified to be a slew-rate detector instead of a rise-time detector. Moreover, the different bigFET response mechanisms under various poweron disturbances are clarified. In addition, the validity of these insights for other designs is also discussed in this paper.

引用

页码：577 / 584

页数：8

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