Experimental Assessment of Electrons and Holes in Erase Transient of TANOS and TANVaS Memories

被引：10

作者：

Suhane, Amit ^{[1
,2
]}

Arreghini, Antonio ^{[1
]}

Van den Bosch, Geert ^{[1
]}

Vandelli, Luca ^{[3
]}

Padovani, Andrea ^{[3
]}

Breuil, Laurent ^{[1
]}

Larcher, Luca ^{[3
]}

De Meyer, Kristin ^{[1
,2
]}

Van Houdt, Jan ^{[1
]}

机构：

[1] IMEC, B-3001 Louvain, Belgium

[2] Katholieke Univ Leuven, ESAT, B-3001 Leuven, Belgium

[3] Univ Modena & Reggio Emilia, DISMI, I-42122 Reggio Emilia, Italy

来源：

IEEE ELECTRON DEVICE LETTERS | 2010年 / 31卷 / 09期

关键词：

Carrier separation; erase transient; TANOS; TANVaS; VariOT;

D O I：

10.1109/LED.2010.2055824

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present carrier separation experiments based on direct charge measurement to assess the contributions of electrons and holes to the erase transient of TANOS-like nonvolatile memories. The role of different carrier species is analyzed as a function of erase voltage and charge configuration at the initial programmed state. We extend the analysis to band-engineered tunneling barriers, demonstrating that the performance improvement in these devices lies more on the enhancement of hole current rather than that of the electron one.

引用

页码：936 / 938

页数：3

共 9 条

[1] Experimental characterization of the vertical position of the trapped charge in Si nitride-based nonvolatile memory cells [J].

Arreghini, Antonio ;

Driussi, Francesco ;

Vianello, Elisa ;

Esseni, David ;

van Duuren, Michiel J. ;

Golubovic, Dusan S. ;

Akil, Nader ;

van Schaijk, Rob .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (05) :1211-1219

[2] QUANTUM YIELD OF ELECTRON-IMPACT IONIZATION IN SILICON [J].

CHANG, C ;

HU, CM ;

BRODERSEN, RW .

JOURNAL OF APPLIED PHYSICS, 1985, 57 (02) :302-309

[3]

DU PY, 2008, P INT REL PHYS S, P399

[4] A consistent model for the SANOS programming operation [J].

Furnemont, A. ;

Rosmeulen, M. ;

Cacciato, A. ;

Breuil, L. ;

De Meyer, K. ;

Maes, H. ;

Van Houdt, J. .

2007 22ND IEEE NON-VOLATILE SEMICONDUCTOR MEMORY WORKSHOP, 2007, :96-+

[5] VARIOT: A novel multilayer tunnel barrier concept, for low-voltage nonvolatile memory devices [J].

Govoreanu, B ;

Blomme, P ;

Rosmeulen, M ;

Van Houdt, J ;

De Meyer, K .

IEEE ELECTRON DEVICE LETTERS, 2003, 24 (02) :99-101

[6]

LAI SC, P VLSI TSA 2007

[7] Study of the erase mechanism of MANOS (Metal/Al2O3/SiN/SiO2/Si) device [J].

Lai, Sheng-Chih ;

Lue, Hang-Ting ;

Hsieh, Jong-Yu ;

Yang, Ming-Jui ;

Chiou, Yan-Kai ;

Wu, Chia-Wei ;

Wu, Tai-Bor ;

Luo, Guang-Li ;

Chien, Chao-Hsin ;

Lai, Erh-Kun ;

Hsieh, Kuang-Yeu ;

Liu, Rich ;

Lu, Chih-Yuan .

IEEE ELECTRON DEVICE LETTERS, 2007, 28 (07) :643-645

[8]

LUE HT, 2007, P IRPS, P177

[9]

VANDELLI L, 2010, P IRPS 2010, P731

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