Inference of message sequence charts

被引:91
作者
Alur, R
Etessami, K
Yannakakis, M
机构
[1] Univ Penn, Dept Comp & Informat Sci, Philadelphia, PA 19104 USA
[2] Univ Edinburgh, Sch Informat, Edinburgh EH9 3JZ, Midlothian, Scotland
[3] Stanford Univ, Dept Comp Sci, Stanford, CA 94305 USA
关键词
message sequence charts; requirements analysis; formal verification; scenarios; concurrent state machines; deadlock freedom; realizability; synthesis;
D O I
10.1109/TSE.2003.1214326
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
Software designers draw Message Sequence Charts for early modeling of the individual behaviors they expect from the concurrent system under design. Can they be sure that precisely the behaviors they have described are realizable by some implementation of the components of the concurrent system? If so, can we automatically synthesize concurrent state machines realizing the given MSCs? If, on the other hand, other unspecified and possibly unwanted scenarios are "implied" by their MSCs, can the software designer be automatically warned and provided the implied MSCs? In this paper, we provide a framework in which all these questions are answered positively. We first describe the formal framework within which one can derive implied MSCs and then provide polynomial-time algorithms for implication, realizability, and synthesis.
引用
收藏
页码:623 / 633
页数:11
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