Interconnects in the third dimension: Design challenges for 3D ICs

被引：66

作者：

Bernstein, Kerry ^{[1
]}

Andry, Paul ^{[1
]}

Cann, Jerome ^{[2
]}

Emma, Phil ^{[1
]}

Greenberg, David ^{[1
]}

Haensch, Wilfried ^{[1
]}

Ignatowski, Mike ^{[1
]}

Koester, Steve ^{[1
]}

Magerlein, John ^{[1
]}

Puri, Ruchir ^{[1
]}

Young, Albert ^{[1
]}

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, Route 134,POB 218, Yorktown Hts, NY 10598 USA

[2] IBM Microelect, Essex Jct, VT 05452 USA

来源：

2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2007年

关键词：

3D; interconnect; through-wafer via; chip-stack; silicon carrier; bandwidth; latency; hierarchical memory;

D O I：

10.1109/DAC.2007.375227

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Despite generation upon generation of scaling, computer chips have until now remained essentially 2-dimensional. Irnprovements in on-chip wire delay and in the maximum number of I/O per chip have not been able to keep up with transistor performance growth; it has become steadily harder to hide the discrepancy. 3D chip technologies come in a number of flavors, but are expected to enable the extension of CMOS performance. Designing in three dimensions, however, forces the industry to look at formerly-two-dimensional integration issues quite differently, and requires the re-fitting of multiple existing EDA capabilities.

引用

页码：562 / +

页数：2

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