A DDR3/4 Memory Link TX Supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with Slew Rate Control and Thin Oxide Output Stages in 22-nm CMOS SOT

A transmitter for data (DQ) lines in a memory link is presented. The transmitter supports a impedance range of 24-40 Omega, operates from a 0.8-1.6 V range, and runs between 0.8 and 5.0 Gb/s. The DDR TX a clock-feathering-based slew rate control with duty adjustment and uses thin oxide output stages for power The power supply for the thin oxide pull-up provided by an on-chip voltage regulator. Also FFE postcursor tap and max. 9.5 dB de-emphasis at 40 SI is Results measured with typical DDR settings such as 30 impedance and 1.35 V supply show a 1.2-5.8 V/ns range into a 50 SI termination, an energy efficiency at of 4.4 pJ/bit and TJ (BER 1012) of 26 ps. The fabricated in 22-nm CMOS SOI and has a size of 132 x 83 mu m(2).